SR Flip-Flop¶

A high level at the Set input sets the output (Q to high, Q- to low) and a high level at Reset input resets the output. If both inputs are reset the output is not changed.

If both Set and Reset are set, the output state depends on the option Set dominant.
If Set Dominant is true, the output is set, when both Set and Reset are high at the same time.
If Set Dominant is false, the output is reset, when both Set and Reset are high at the same time.
If Positive edge triggered is active, the state changes only occur at positive input edges otherwise the static values are decisive. With positive edge triggering there is no output change if the inputs fall from 1 to 0.

The logic initial value is selectable.

The output can be delayed by one integration step by setting propagation delay.

Q0 = level of Q before the last change of Set or Reset.