D Flip-Flop¶

The D-type flip-flop has asynchronous Set and Reset inputs and complementary (Q,Q-) outputs. Information at the input is transferred to the outputs on the positive going edge of the Clock Pulse. After the Clock Pulse the Data input is locked out and information present will not be transferred to the outputs until the next rising edge at the Clock Pulse input.

The logic initial value is selectable.
The output can be delayed by one integration step by setting propagation delay.