JK Flip-Flop¶

A high level at Set or Reset input sets or resets the outputs regardless of the levels of the other inputs. When Set and Reset are inactive (low), data at the J and K inputs are transferred to the outputs on the positive-going edge of the clock pulse. Data at J and K input may be changed without affecting the levels at the outputs. This flip-flop can be used as toggle flip flop by tying J and K high.

The logic initial value is selectable.

The output can be delayed by one integration step by setting propagation delay.

X = don't care

Q0 = level of Q before the last input change or clock pulse

= 0-1 CP edge