Logic - Introduction¶

Logic elements perform Boolean operations with binary and logical signals. In SimApp, there is no difference between logic and analog signals. Logic elements can be supplied by output signals of analog elements and vice versa.

Input signals lower than the logic threshold are interpreted as low (logic 0 or false) whereas signals being greater than the logic threshold are interpreted as high (logic 1 or true). The default threshold value is 0.5 and default logic high output value is 1. Logic 0 is always 0.

Feedback with logic elements
By default, logic elements in SimApp have no propagation delay. Thus, there are the same restrictions as for other elements: Feedback loops without any delay elements are not allowed (see algebraic loops).

However, in logic circuits it is common to build feedback loops. For example you can form a set/reset flip flop with two NAND gates in a feedback configuration.

Furthermore, logic circuits often need propagation delays for proper operation, even when they do not have feedback loops. For example, in a synchronous counter with a chain of JK flip-flops all having the same input clock signal, it is essential that the states at the J and K inputs and the outputs of the preceding flip-flops, change after the positive going edge of the clock signal. For details, see the counter example in the programs example directory.

To enable such cases, all logic elements have the option Propagation delay. The output signal of the element changes only at the beginning of the next integration interval if this option is set. Therefore, a short delay of one integration step size can be included. If the integration step size is set as recommended (see chapter Time simulation) this delay can be neglected. If you build large logical circuits or long chains of logic elements the sum of delays may become unacceptable long.

If you encounter such problems, you can take the following actions.

1. Enable the Propagation Delay option only for one logic element in the feedback loop.
   2. Reduce the integration step size by factor 10.